To realize miniaturization and high-density packaging of the semiconductor device, a stacked semiconductor device (semiconductor package) having plural semiconductor elements stacked and sealed in one package has been realized. In the stacked semiconductor device, the plural semiconductor elements are sequentially stacked on a wiring board or a circuit board such as a lead frame via an adhesive layer. The electrode pads of the semiconductor elements are electrically connected via the metallic wires and the connection pads of the circuit substrate. Thus, the stacked semiconductor is configured by sealing the laminated body with a resin.
For example, a memory card (semiconductor memory card) having a NAND-type flash memory therein is being downsized and provided with high capacity rapidly. For realization of a downsized memory card, a semiconductor element such as a memory element or a controller element is mounted in a stacked form on a wiring board. The electrode pads of the semiconductor element are electrically connected to the connection pads of the wiring board by wire bonding. Besides, to provide the memory card with high capacity, the memory elements have come to be also stacked into multiple layers on the wiring board.
The front surface of the semiconductor element is covered with an insulating protection film, but an outer peripheral portion of the front surface is not covered with the insulating protection film, so that a semiconductor substrate and a wiring layer configuring the semiconductor element are exposed on the corners between the front surface and the sidewall surface. In a case where wire bonding is applied to the semiconductor element, it is necessary to perform wiring of the metallic wires while keeping a loop height such that they do not come into contact with the corners of the semiconductor element. The stacked semiconductor device is demanded that the laminate thickness of plural semiconductor elements and therefore the package thickness are reduced. Meanwhile, the loop height of the metallic wires connected to the semiconductor elements of the top layer becomes a cause of increasing the package thickness.
Specifically, the metallic wires connected to the semiconductor elements on the top layer are arranged so as to inevitably pass through portions which exceed the laminate thickness of the plural semiconductor elements. In a case where the laminated body of the semiconductor elements having the metallic wires in the above described form is sealed with a resin, the sealing resin is required to have a thickness equivalent to the shapes of the wires connected to the semiconductor elements of the top layer. Thus, the package thickness is caused to be made large. Besides, the metallic wires distributed while keeping the loop height have a disadvantage that wire sweep is easily caused at the time of resin sealing. The wire sweep becomes a cause of inducing a short circuit because of a contact between adjacent wires having different potentials.
JP-A 2000-307036 (KOKAI) describes that a resin block is arranged on a substrate to cover a part and the sidewall surface of an electrode formation surface of a semiconductor element so as to prevent a contact between the corners of the semiconductor element and the metallic wires. In a case where the semiconductor elements are stacked into multiple layers, the resin block cannot prevent the contact of the metallic wires with the semiconductor elements. JP-A 2001-244281 (KOKAI) describes that a protection resin layer is formed on a sidewall surface and a back surface (surface opposite to the bump electrode-formed surface) of a flip-chip mounting semiconductor element. Here, a multilayer lamination of the semiconductor elements is not taken into consideration because the flip-chip mounting semiconductor element is under consideration.
Besides, there is a tendency that the number of memory elements stacked on the memory card is increased. For example, it is being studied to stack into four, eight or more layers depending on the storage capacity of the memory card. To stack the semiconductor elements into multiple layers, it is necessary to reduce the thickness of each element. When the wire bonding is applied to the semiconductor elements having a reduced thickness, the semiconductor elements might be damaged by a bonding load. Accordingly, it is being studied to stack the plural semiconductor elements into a step-like shape to expose the electrode pads and to electrically connect between the electrode pads of the plural semiconductor elements and between the electrode pads and the connection pads of the wiring board with a conductive layer (see JP-A 2004-063569 (KOKAI) and JP-A 2005-302763 (KOKAI)).
In a case where plural semiconductor elements are simply stacked to have a step-like shape, a length in the stepped direction becomes long with the increase in the number of stacked semiconductor elements, and an occupied area of the semiconductor elements to the wiring board increases. Meanwhile, the occupied area of the semiconductor elements to the wiring board can be decreased by stacking the plural element groups, which have the semiconductor elements stacked to have the step-like shape, via a spacer layer, or stacking the plural element groups in a direction opposite to the stepped direction. Though the conductive layer can be applied to the connection between the electrode pads in the element groups, it becomes hard to connect the semiconductor elements of the element group located at a higher position with the wiring board by the conductive layer.
For electrode pads having the same electric properties and signal characteristics, the electrode pads of plural semiconductor elements stacked to have a step-like shape can be connected sequentially by the conductive layer. But, for electrode pads for control signals to perform chip select, the individual electrode pads of the plural semiconductor elements are occasionally required to be connected to the connection pads of the wiring board according to the control signals. Such a connection structure can be realized by wire bonding of metallic wires at an incidence angle. But, for connection between the semiconductor element and the wiring board, it is hard to connect the electrode pads of the plural semiconductor elements to the connection pads respectively by applying a conductive layer.